1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and more particularly to an electrically erasable programmable read-only memory (EEPROM).
2. Description of the Related Art
In such a memory cell constituting an EEPROM shown in FIGS. 22A and 22B, one-device type MOS memory having a control gate 1 and a floating gate 5 is electrically insulated by a gate oxide film 3 and an insulating oxide film 4, and is disposed between the control gate 1 and a semiconductor substrate 2 immediately below the control gate. Though an advantage of the one-device type memory is that its cell size can be made small, various kinds of the memory devices provided with improved methods for injection of electrons into the floating gate or for attraction of electrons from the same have been developed as described below.
According to a first method, as depicted in FIG. 22A, writing of data to a selected memory is achieved by applying a high bias voltage to a drain conjunction to generate a CHE (Channel Hot Electron) at an end portion of a drain region 6 and by injecting the CHE into the floating gate through the thin gate oxide film 3. Erasing of data, as shown in FIG. 22B, is achieved by attracting electrons accumulated in the floating gate 5 to a source region 7 by FN (Fowler Nordheim) tunnel currents (as disclosed in, for example, Japanese Laid-open Patent Application No. Sho64-81272, and as published in International Electronic Device Conference Technical Digest, PP.616 to PP.619).
According to a second method, the method for writing data to a selected memory cell is, as shown in FIG. 23A, the same for the first method in that it is achieved by injecting the CHE generated at the end portion of the drain region into the floating gate 5 through a thin gate oxide film 3. However, erasing of data, as shown in FIG. 23B, is achieved by attracting electrons accumulated in the floating gate to a semiconductor substrate 2 disposed immediately below the floating gate through the gate oxide film 3 by FN tunnel currents.
Moreover, according to a third method, writing of data to a selected memory cell is, as shown in FIG. 24A, achieved by attracting electrons accumulated in a floating gate 5 to a drain region 6 or a source region 7 by FN tunnel currents. However, erasing of data, as shown in FIG. 24B, is achieved by injecting electrons from a semiconductor substrate 2 to the floating gate through a gate oxide film 3 by FN tunnel currents.
On the other hand, as shown in FIGS. 25A and 25B, a two-device type memory cell, which is intended to improve writing and erasing characteristics of each memory cell, is known as wherein, a MOS transistor for switching (a switch transistor 10 in the drawing) is connected serially to a source of a floating-gate type MOS transistor (memory transistor 8) (for example, in U.S. Pat. No. 5,646,060).
In the two-device type memory cells, as shown in FIG. 25A, writing of data to a selected memory cell is achieved, with a switch transistor 10 turned off, by applying a voltage of 8 V to a control gate 11 of a memory transistor 8 and 6 V (being lower than a control gate voltage) to a drain terminal and by injecting a CHE from a drain region 12 to a floating gate 13 (see FIG. 25A), while, erasing of data is achieved by applying a voltage of -10 V to the floating gate 13 and 5 V to the drain terminal, thereby attracting electrons from the floating gate 13 to the drain region 12 by FN tunnel currents (see FIG. 22B). Furthermore, to read data from a selected memory cell, with a switch transistor 10 turned on, a voltage of 0 V is applied to a source terminal, a power supply voltage VCC to a control gate terminal and 1 V to a drain terminal respectively, and whether the read data is a "0" or a "1" is judged depending on the flow or non-flow of currents through the memory cell. At this point, a voltage of 0 V is applied to a control gate terminal of an non-selected memory cell.
However, the conventional semiconductor memory device described above has a shortcoming in that its reading speed is low because the control gates 1 and 11 are used to control a voltage in writing, erasing and reading operations. That is, in writing or erasing operations, to inject electrons from the control gates 1 and 11 by FN tunnel currents or to attract electrons by FN tunnel currents, the control gates require high voltages and therefore, as shown in FIGS. 26 and 27, a high voltage control circuit is connected to the control gates 1 and 11. However, to read data, the high voltage is not required and therefore a row decoder is composed of a normal voltage circuit 15. Because these two outputs from the high voltage control circuit and from the normal voltage circuit are used to control a voltage of the same control gates 1 and 11, these two circuits are conventionally connected to the control gates 1 and 11. However, to protect the normal voltage circuit 15 having less withstand capability, a voltage relaxation circuit 16 is interposed between the normal voltage circuit 15 and the high voltage control circuit 14. The insertion of the voltage relaxation circuit and great parasitic capacity of the high voltage control circuit 14 interfere with high-speed operations.
In addition, because the voltage relaxation circuits with the same numbers as those of word lines are required, the number and area of devices to be used for, in particular, two-device type memory cells increase accordingly.
There is a method to control the control gate voltage Vcg by using only the high voltage generating circuit in the operations of read data, however, such high voltage generating circuits are usually composed of a high voltage withstand transistor which uses thick gate oxide films and has increased gate length to raise its withstand capabilities. Accordingly, to obtain a predetermined on-current, it is necessary to increase a gate width, resulting in an increase of parasitic capacity. However, because of this, the operational speed of the high voltage circuit is remarkably low compared with that of the normal voltage circuit, thus interfering with high-speed reading.
Moreover, in the conventional semiconductor memory devices described above, an operational principle is employed that, at the time of read data, a voltage of the control gate is changed depending on selection or non-selection. However, whenever the voltage is changed, voltage stress is generated, causing the deterioration of data holding characteristics of the floating gate. As shown in Table 1, the conventional floating gate, when a "0" is written, is at a potential of, for example, -1 V and when a "1" is written, is at a potential of, for example, +1 V. If reading of data is to be achieved by applying, for example, 5 V to the control gate of a selected memory cell, the potential state of the floating gate is changed from -1 V to, for example, 0 V, or from +1 V to, for example, +2 V. This means that the potential of the floating gate varies in a great range between -1 V and +2 V, causing a large voltage stress.
TABLE 1 ______________________________________ Non-selected Selected ______________________________________ Control Writing of Writing of Writing of Writing of gate "0" "1" "0" "1" 0 0 5 5 Floating -1 +1 0 2 gate ______________________________________
As described above and shown in FIG. 28, due to the fact that the control gate voltage Vcc is changed depending on selection and non-selection at the time of read data, there is a problem in that a threshold voltage Vt of an erasing cell is controlled so as to narrow the range of voltages.
Another problem is that, because a considerably large drain current must be passed to perform writing operations by injecting the CHE from the drain region to the control gate, power consumption is made large and a charge pump having a large device area is required.
A further problem is that, because a high electric field in the drain region (or source region) is generated when electrons are attracted from the floating gate to the drain by FN tunnel currents, the band is made narrow in the vicinity of the PN junction region and of an interface between the gate oxide film and the drain region (or the source region), causing a tunnel current between bands by holes or electrons to flow, holes to be injected to the gate oxide film or the floating gate, and over-erasing or over-writing to occur which leads to an improper reading.
Another problem is that, when the CHE is injected from the drain region to the control gate or when electrons are attracted from the floating gate to the drain region (or the source region) by FN tunnel currents, the injection or attraction at a one-sided portion of the floating gate takes place, causing local damage to the gate oxide film and a breakdown of a device.